Multi-Band Outphasing Power Amplifier Design for Mobile and Base Stations

New generations of wireless communication systems require linear efficient RF power amplifiers (PAs) for higher transmission data rates and longer battery life. On the contrary, conventional PAs are normally designed for peak efficiency under maximum output power (Pout). Thus, in power back-off, the overall efficiency degrades significantly and the average efficiency is much lower than the efficiency at maximum Pout. Chireix outphasing PA, also called LINC (Linear amplification using Non-linear Components), is one of the most promising techniques to improve the efficiency at power back-off. In this method, a variable envelope input signal is first decomposed into two constant-envelope phase-modulated signals and then amplified using two highly efficient non-linear PAs. The output signals are combined preferably in a loss-less power combiner to build the desired output signal. In this way, the PA exhibits high efficiency with good linearity. In this thesis, first we analyze a complex model of outphasing combiner considering its nonidealities such as reflection and loss in transmission lines (TL). Then we propose a compact model with analytical formula that is validated through several comparative tests using ADS and Spectre RF. Furthermore, we analyze the effect of reactive load in Chireix combiner with stubs (a parallel inductor and capacitor), while distinguishing between its capacitive and inductive parts. It is demonstrated that only the capacitive part of the reactive load degrades the performances. Based on this, a new architecture (Z LINC) is proposed where the power combiner is designed to provide a zero capacitive load to the PAs whatever the outphasing angle. The theory describing the operations of the system is developed and a 900 MHz classical LINC and Z-LINC PAs are designed and measured. In addition, a miniaturization technique is proposed which employs λ/8 or smaller TLs instead of conventional λ/4 TLs in outphasing power combiner. This technique is applied to implement a 900 MHz PA using LDMOS power transistors. Besides single-band PAs, dual-band PAs are more and more needed because of an increasing demand for wireless communication terminals to handle multi-band operation. In chapter 5, a new compact design approach for dual-band transmitters based on a reconfigurable outphasing combiner is proposed. The objective is to avoid the cumbersome implementations where several PAs and matching network are used in parallel. The technique is applied to design a dual band PA with a fully integrated power combiner in 90 nm CMOS technology. An inverter-based class D PA topology, particularly suitable for outphasing and multimode operations is presented. The TLs in the combiner, realized using a network of on-chip series inductors and parallel capacitors, are reconfigurable from λ/4 in 1800 MHz to λ/8 in 900 MHz. In order to maximize the efficiency, the on-chip inductors are implemented using high quality factor on chip slab inductors. The measured maximum Pout at 900/1800 MHz are 24.3 and 22.7 dBm with maximum efficiencies of 51% and 34% respectively

On Gm-boosting and cyclostationary noise mechanisms in low-voltage CMOS differential Colpitts VCOs

This paper presents a theoretical study of CMOS differential Colpitts VCOs. The objective is to provide a deep understanding of the different mechanisms that impact the performances of these VCOs, namely the Gm-boosting and cyclostationary noise. The developed methodology and expressions can be used to analyze, optimize and build new VCO topologies. A novel topology with an optimized gate to source (GS) feedback is proposed. It exhibits a figure of merit (FOM) better than -190 dBc/Hz/mW for all the frequency offsets

Analysis and Modeling of On-Chip Power Combiners and Their Losses in LINC Transmitters

This paper presents a compact model for LINC (linear amplification with non linear components) transmitters an their power combiners. The study focuses on the detrimental effect of the transmission line nonidealities. A mathematical description of the system that considers these nonidealities is proposed. The developed analytical expressions can be used to optimize, analyze and build pre-distortion algorithms for this family of transmitters. The efficiency and linearity are reexamined in light of the new analytical expressions of the model

A Zero Capacitive LINC Architecture for Efficient Broadband Transmitters

A new approach for linear amplification with nonlinear components (Z-LINC) that provides a zero capacitive load to their power amplifiers is proposed. The zero capacitive loading over the whole power back-off range enables to overcome the efficiency deterioration. The concept is theoretically and experimentally validated through a comparative study between fabricated classical LINC and Z-LINC prototypes

A 10-W modified LINC Power amplifier with a reduced-size Chireix Power Combiner

This paper reports a miniaturization technique of non-isolated power combiners and its application for a compact outphasing transmitter. The technique is used to build an LDMOS Z-LINC system. The maximum output power and PAE measured at 900 MHz are 9.3 W and 70 % with a size reduction of around 50 %. PAE at 3 and 6 dB power back-off are 63 % and 45 % respectively

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a die to achieve upward or downward scalability, or connecting to an off-chip SerDes or optics engine. Each of these in-package applications typically has high throughput and onerously low power constraints along with a low-loss channel. Several solutions have been proposed. Interposer substrates [1], or Chip-on-Substrate-on-Wafer [2] allow for very high-density wiring and low power using CMOS transceivers. Their high manufacturing and testing cost makes them prohibitive for anything but high-end applications. A different approach using high-speed ground-referenced single-ended signaling is reported in [3], which is intended for shorter channels up to 4.5mm and a BER of 1e-12. An approach using differential signaling on up to 0.75" of Megtron 6 material and a BER of 1e-9 is reported in [4]. A comparison is given in Fig. 10.1.1